The present invention relates to an analog signal amplifier circuit integrated on a semiconductor integrated circuit and, more specifically, to an analog signal amplifier circuit using a differential pair of MOSFETs (insulated-gate field effect transistors) in an input stage.
In most prior art semiconductor integrated circuits, a voltage-amplitude limiter circuit (limiter amplifier) and a voltage comparator circuit (comparator) for amplifying an analog signal, which are called an analog signal amplifier circuit, are each constituted of a bipolar transistor.
The trend is to constitute an analog signal amplifier circuit using MOS transistors in place of bipolar transistors with recent technological advances. However, the mutual conductance gm of a MOS transistor is smaller than that of a bipolar transistor and has a characteristic that it is proportionate to both the (1/2)th power of a drain current and the (1/2)th power of the ratio of gate width to gate length of the transistor. Therefore, an analog signal amplifier circuit using a differential pair of PMOS transistors M1 and M2 in an input stage, as shown in FIG. 1, has the following problem.
If the mutual conductance gm of the above PMOS transistors M1 and M2 is tenfold in order to achieve a high gain, the drain current or the gate width should be increased hundredfold in view of the above characteristic, which produces a bad effect of greatly increasing the current consumption and the area of an integrated circuit. Such an amplifier circuit is thus impractical.